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Design for testability - DFT

VLSI Design for Test (DFT) Training program comes with offline and online  course a comprehensive course designed to equip participants with the knowledge and skills necessary to excel in the field of Very Large Scale Integration (VLSI) testing. VLSI DFT is a critical aspect of semiconductor design, ensuring that complex integrated circuits are manufactured with high reliability and functionality.

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Eligibility Criteria For Design for Testability Online/Offline Course.

  • B.Tech/M/Tech degree in Electronics & Communication (ECE), Electrical & Electronics (EEE), or closely related fields.
  • B,Tech/M.Tech in Computer Science (CSE) or Closely related Fields
  • M.Tech in VLSI or closely related fields

Course Curriculum

  1. Logic Gates
  2. Boolean Algebras, Boolean Expression and K-Map
  3. Combinational Circuits:- Adders, Subtractors, Multiplexer, De-multiplexer, Encoders, Priority Encoder, Decoders, Comparator, and converters.
  4. Sequential Circuits: Latches, Flip-Flops, Registers and Counters.
  5. Finite State Machines.
  1. All Basic Gates
  2. Adders and Encoders
  3. Multiplexers
  4. D- Flip flop, Latches, Synchronous reset and Asynchronous reset, Scan flop, Clock gating circuit and Divide by 2 circuits.
  5. Registers and Counters
  1. Basics of DLD
  2. Overall VLSI flow
  3. History, need and introduction to DFT
  4. DFT Flow at high level
  5. Hardware elements : PLL, Divider, Clock gater, Latch, TDR
  6. Defect, Fault, Fault modelling & Error difference
  7. Timing and its role in DFT
  8. Basic UNIX commands
    1. Intro : Basic flow and Architecture
    2. Scan insertion types
    • Internal Scan
    • Boundary Scan

     

    1. Scan methodology
    2. Choosing parameters
    3. Chain balancing
    4. Library cells
    5. Types of scanned Flip-flops
    • MUX-D
    • LSSD
    1. Clock and edge mixing
    2. DFT rules check
    3. Scan input and output files
    4. Scan Chain re-ordering
    5. Common issues in Scan insertion
    1. Need for Compression
    2. Compressor
    3. Decompressor
    • Ring oscillator
    • Phase shifter
    1. LFSR,LFSM
    2. Compression ratio
    3. Masking logic
    4. Internal scan chains
    5. Adding sub chains
    6. Scan chain Re-order
    7. EDT control signals
    8. EDT clock and EDT update
    9. EDT bypass logic
    10. EDT lockup- latch/Terminal lockup-latch
    11. Compression ratio
    12. Faults inside EDT
  • What is ATPG?
  • Basic flow – inputs, process and outputs
  • Sequential depth
  • Fault models – Stuck, Transition and path delay
  • Fault identification/sensitization
  • Fault propagation and justification
  • Fault categories
  • Test procedures
  • LOS vs LOC
  • Coverage – Test and fault coverage
  • Coverage Debug
  • SDC in ATPG
  • Test time and test volume
  • Fault grading
  • SDC delivery for DFT modes
  •  
  1. What is OCC
  • Advantages
  • Dis advantages
  • Internal structure of OCC
  1. Simulations introduction and why we need
  2. Simulation flow
  3. Tools for simulation
  4. Simulations types
  • Serial simulations
  • Parallel simulations
  1. Scan simulation debugging
  2. Chain simulation debugging
  3. Timing & no timing simulations with differences?
  4. Patten failure debugging with simulation and ATPG
  • Intro to MBIST
  • Intro to 1149.1 and TAP
  • Intro to Bscan
  • Intro to LBIST
  • Intro to diagnosis
  • Conclusion
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